In the fabrication of semiconductor devices, P.sup.- and N.sup.- type doped regions in single crystal and polycrystalline silicon are formed as active devices. The doped regions form the basic elements of a semiconductor device which must be connected in a specific configuration to form a desired circuit. The circuit must then be accessible to the outside world through conducting pads for testing with metal probes and for bonding into a packaged chip. While doped silicon and polysilicon conduct electricity, they are not useful in forming contacts or interconnects due to their prohibitively large resistance. As a result, at least one low-resistance contact material such as metal must be deposited and patterned to contact the different regions in a chip.
It is known that when contact is made between two dissimilar materials, a contact potential in the form of a barrier typically develops at an interface between the materials. Such a contact formed between a metal and a semiconductor can be categorized as an ohmic contact which ideally is transparent to current and thus allowing a linear current-voltage characteristic with negligible resistance in both directions across the contact. In order to make sub-micron contacts of sufficiently low resistance, surface dopant concentrations of greater than 10.sup.20 cm.sup.-3 are normally required for achieving a resistance that approaches an ideal ohmic contact so that current may pass with little resistance.
In modern semiconductor devices, specifically those fabricated by the ULSI or the sub-half-micron technology, the depth of the junctions formed in a silicon substrate is reduced when the total dimensions of the device are reduced. One potential problem encountered in reducing the depth of the junctions is the inevitable increase in the sheet and contact resistances of the junctions. A known method for reducing the sheet and contact resistances of junctions, specifically when used in conjunction with a polysilicon contact, is the use of metal silicides for reducing these resistances. Barrier metals are normally deposited on the silicides in order to protect the silicide films and the interfaces with silicon from diffusing species during subsequent processing steps.
Metal silicides can be used in such microelectronic applications by reacting refractory or near noble metals with silicon. Among the more popularly used metal silicides in microelectronics are titanium silicides (TiSi.sub.2), cobalt silicide (CoSi.sub.2), tungsten silicide (WiS.sub.2), platinum silicide (PtSi), molybdenum silicide (MoSi.sub.2), palladium silicide (PdSi) tantalum silicide (TaSi.sub.2), and chromium silicide (CrSi). When used in conjunction with a polysilicon layer, the silicide films deposited in parallel with the higher-resistivity junction reduces resistance in the transistor regions. The combined metal silicide/polysilicon metallurgy (sometimes called a polycide) presents a major benefit that it can withstand processing temperatures of higher than 550.degree. C., for instance, a reflow temperature of 850.degree. C. during a planarization process for PSG or BPSG. Such high processing temperatures normally cannot be tolerated by other contact materials. Among the different metal suicides, tungsten silicide, titanium silicide and cobalt silicide are the more commonly used materials based on their low resistivity and their stability in contacts with polysilicon gates and junctions.
Enlarged cross-sectional views of the formation of a metal silicide on a polysilicon gate by a conventional method is illustrated in FIGS. 1A.about.1C. A conventional self-aligned silicidation process for a post-junction-formation silicide performed on a semiconductor device 10 is shown in FIG. 1A. Onto a silicon substrate 12, LOCOS insulators 14 and 16, lightly doped drain regions 18 and 20, a polysilicon gate 22, and gate oxide 24 are first formed by conventional methods. Oxide sidewall spacers 26, 28 for protecting the polysilicon gate 22 are then formed. An ion implantation process is used to form junctions 32, 34 for the source/drain regions. The structure formed in FIG. 1A is representative of a typical self-aligned TiSi.sub.2 process.
In the next step of the process wherein metal silicide layer is formed, various techniques such as sputtering, evaporation or chemical vapor deposition can be used to first deposit a metal layer 40 over the polysilicon gate 22 and the exposed single crystal silicon regions. In the present example of TiSi.sub.2, a titanium layer 40 is deposited and then annealed by a two-step furnace or rapid thermal annealing process. In the first step, the titanium film is annealed at a temperature of 650.degree. C. in a nitrogen atmosphere such that titanium nitride is formed at the surface of the metal while titanium reacts with silicon and forms TiSi.sub.2 in those regions where titanium contacts with silicon. At the annealing temperature of 650.degree. C., a high resistivity TiSi.sub.2 forms readily in the exposed silicon regions, while a negligible reaction between titanium and silicon occurs where the metal is in contact with silicon dioxide or silicon nitride insulators. The metal composition in contact with the insulators consists mainly of TiN and unreacted Ti which are then removed by a wet dipping process leaving the metal silicide layer intact. The process results in a self-alignment between the silicide and the exposed silicon regions and therefore, is called a salicide process indicating that silicides formed over polysilicon and single crystal silicon are self aligned to each other. A second annealing step for the TiSi.sub.2 is necessary which is typically conducted at a temperature of 800.degree. C. to further transform the silicide to a lower resistivity phase. The metal silicide region 42 over the polysilicon gate 22, and the metal silicide regions 44, 46 formed over the single crystal silicon regions 32, 34 are shown in an enlarged, cross-sectional view in FIG. 1C.
The conventional method for forming metal silicide layers over a polysilicon gate and single crystal silicon source/drain regions shown in FIGS. 1A.about.1C presents several processing problems. The processing problems occurring in the self-aligned silicide formation process are the formation of a bridge between gate and the source/drain regions, the difficulty in forming silicide on thin layer of polysilicon and shallow diffusion regions, and the thermal stability of thin metal silicides formed. Of these problems, the bridging between a gate and source/drain regions is the most serious. For instance, in the formation of TiSi.sub.2, it is known that silicon is the predominant diffusion species that moves through a growing silicide phase to react with the metal. As a result, TiSi.sub.2 formation is no longer confined to where Ti contacts Si. For instance, TiSi.sub.2 may readily form along the sidewalls of the gate insulators resulting in a short between the gate and the source/drain regions. It has been observed that, under favorable conditions, silicon can diffuse a long distance and thus forming TiSi.sub.2 on the sidewall spacers. The extent of the bridge formation is determined by the temperature and the duration of the sintering process occurring between metal and silicon. Since a high temperature of at least 600.degree. C. is normally required to cause a reaction between Ti and Si for the sintering of TiSi.sub.2, an extensive diffusion of Si in Ti already occurs at such high temperature. Even though efforts have been made to reduce the bridging problem by utilizing a nitrogen atmosphere and by utilizing a rapid thermal process to reduce the heating time, these efforts have only met limited success and works only up to a temperature of about 680.degree. C.
It is therefore an object of the present invention to provide a method for forming metal silicide on an electronic device that does not have the drawbacks or shortcomings of a conventional silicide formation method.
It is another object of the present invention to provide a method for forming metal silicide on an electronic structure that does not require the use of an extended high temperature exposure such as that conducted in a furnace or in a rapid thermal process.
It is a further object of the present invention to provide a method for forming metal silicide on an electronic structure by irradiating a metal layer deposited on a silicon surface with an energy source for a sufficient length of time.
It is another further object of the present invention to provide a method for forming metal silicide on an electronic structure by first depositing a metal layer on top of a silicon layer and then irradiating the metal layer with laser energy until a layer of metal silicide is formed at the metal/silicon interface.
It is still another object of the present invention to provide a method for forming metal silicide on an electronic structure by first irradiating a metal layer deposited on top of a silicon layer with a laser energy and then removing unreacted metal layer to leave a low resistivity metal silicide layer.
It is yet another object of the present invention to provide a method for forming a metal silicide layer on a thin film transistor structure by first depositing a metal layer of an amorphous silicon layer and then irradiating the metal layer with laser energy until a metal silicide layer is formed at the metal/amorphous silicon interface.
It is still another further object of the present invention to provide a method for forming metal silicide on a silicon substrate by first depositing a metal layer on top of a polysilicon layer and then irradiating the metal layer with laser energy for a sufficient length of time such that a metal silicide layer is formed at the metal/polysilicon interface.
It is yet another further object of the present invention to provide a method for forming metal silicide on a silicon substrate by first depositing a metal layer on top of a single crystal silicon layer and then irradiating the metal layer with laser energy for a sufficient length of time such that a metal suicide layer is formed at the metal/single crystal silicon interface.